1 Technical Field of the Invention
The present invention relates generally to a DSV (Digital Sum Value) control system for DSV control in conversion of m-bit digital data codes into n-bit digital modulation codes using a plurality of modulation tables.
2 Background of Related Art
U.S. Pat. No. 5,638,064 to Mori et al., issued Jun. 10, 1997, assigned to the same assignee of this application, discloses a digital modulating/demodulating system which converts a sequence of m-bit data codes into a sequence of n-bit modulation codes using a single modulation table and, if one of the n-bit modulation codes meets a specified condition, changes it with another code for controlling a DSV of the sequence of n-bit modulation codes.
FIG. 3 shows a conventional DSV control system, as taught in Mori et al. In the following discussion, modulation codes into which digital data codes are converted using a modulation table (not shown) are, as shown in FIG. 4(a), expressed by D0, D1, D2, Modulation codes provided at the same address for DSV control are expressed by additional characters "m" and "n", respectively, which will be referred to as DSV control enable codes hereinafter. A modulation code sequence D0, D1, D2, D4, D5m, D6, . . . is generally expressed by "Dm", while a modulation code sequence D0, D1, D2, D4, D5n, D6, . . . is generally expressed by "Dn". "D" indicates one-byte data code.
The modulation code sequences Dm and Dn are supplied to memories 10 and 12. Each of the memories 10 and 12 includes a frame memory wherein 93 bytes are assigned to one frame, and data on a preceding frame is read out of a memory location specified by an address outputted from the address counter 14, while data on a current frame is written therein. Specifically, the data on a preceding frame is read out from each of the memories 10 and 12 during the first half of a period of time within which one-byte data is processed, and the data of a current frame is written during the second half.
The modulation code sequences Dm and Dn are also inputted to the DSV comparator 16. The DSV comparator 16 calculates DSVs of the modulation code sequences Dm and Dn every input of the modulation codes, respectively, to determine which of them is smaller and provides to the memory 18 a select signal indicating which of the modulation code sequences Dm and Dn should be selected. The memory 18 reads a select signal for a preceding frame out of a memory location specified by an address supplied from the address counter 14 and writes a select signal for a current frame in a memory location at a pointer address specified by the pointer register 20. Specifically, the select signal for a preceding frame is read out during the first half of a period of time within which one-byte data is processed, and the select signal for a current frame is written during the second half. The addresses supplied from the address counter 14 and the pointer addresses supplied from the pointer register 20 are different from each other.
The pointer register 20 consists of, for example, an enable latch circuit which latches an address supplied from the address counter 14 as an enable signal when a DSV control enable flag outputted from the DSV control decision circuit 22 indicates logical one (1) meaning that a DSV can be controlled. The data selector 24 is responsive to the select signal from the memory 18 to select one of data outputs from the memories 10 and 12 and outputs it.
The modulation code sequence, as shown in FIG. 4(a), will be discussed below in detail. In this example, DSV control enable modulation codes appear at address Nos. 5, 10, 15, . . . . The DSV control decision circuit 22 outputs a DSV control enable flag of one (1) at each of address Nos. 4, 9, 14, . . . , one byte before the address Nos. 5, 10, 15, (see FIG. 4(d)). The pointer register 20 is responsive to input of the DSV control enable flag of one (1) to latch, as shown in FIG. 4(c), an address supplied from the address counter 14. Specifically, address Nos. 5, 10, 15, . . . are latched and outputted as pointer addresses to the memory 18.
The DSV comparator 16 compares a DSV of a sequence of the modulation codes up to the address No. 9 when the modulation code D5m is selected at the address No. 5 with a DSV of a sequence of the modulation codes up to the address No. 9 when the modulation code D5n is selected at the address No. 5 and outputs a select signal for selecting the smaller one to the memory 18. The memory 18 receives the select signal and writes it at the pointer address No. 5 when the address No. 9 is reached. For example, when the modulation code D5m is selected at the address No. 5, logical zero (0) is written as a select signal in the pointer address No. 5. Alternatively, when the modulation code D5n is selected, logical one (1) is written as the select signal in the pointer address No. 5.
In this manner, the selection of one of the DSV control enable modulation codes D5m and D5n is achieved one byte ahead of the DSV control enable modulation codes D10m and D10n under feedback control. Note that select signals for all codes other than the DSV control enable modulation codes may be either of logical zero (0) and one (1) and stored as zero (0), for example.
In a data read out operation, the modulation code sequences Dm and Dn of a preceding frame are read out of the memories 10 and 12 according to addresses supplied from the address counter 14, while those of a current frame are stored therein. The modulation code sequences Dm and Dn read out of the memories 10 and 12 are supplied to the data selector 24. The select signals are read, in sequence, out of the memory 18 at the addresses supplied from the address counter 14 and outputted to the data selector 24.
The data selector 24 is responsive to the select signal from the memory 18 to select one of the codes of the modulation code sequence Dm or one of the codes of the modulation code sequence Dn and outputs it. For example, when the select signal shows, as shown in FIG. 4(e), logical zero (0) at the address No. 5, an output of the memory 10 is selected, and the DSV control enable modulation code D5m is outputted. Additionally, when the select signal shows the logical one (1) at the address No. 10, an output of the memory 12 is selected, and the DSV control enable modulation code D5n is outputted.
The conventional DSV control system, as described above, controls a DSV by changing a portion of a n-bit digital modulation code sequence, into which a m-bit digital code sequence is converted using one modulation table, with a specific modulation code meeting a given condition. It is, however, impossible to use this technique with, for example, a DVD (Digital Video Disc) system which produces a plurality of modulation code sequences using a plurality of modulation tables. This is because it is necessary to provide select signals one for each code of the modulation code sequences.
FIGS. 2(a) and 2(b) show, as examples, a main modulation code sequence and a sub-modulation code sequence which are converted using modulation tables under the DVD standards. The main modulation code sequence consists of codes M1, M3, M2, M4, M3, . . . . The sub-modulation code sequence consists of codes M2, M3, M2, M1, M2, . . . . The modulation code sequences Dm and Dn, as shown in FIGS. 4(a), are identical with each other except for the DSV control enable codes. Thus, the select signals may be set either to logical one (1) or zero (0) except those for the DSV control enable codes. However, in the examples, as shown in FIGS. 2(a) and 2(b), the main modulation code sequences and the sub-modulation code sequences are different from each other. It is, therefore, necessary to specify logical values of select signals one for each code of the main and sub-modulation code sequences. Specifically, it is impossible to use the above conventional DSV control system with DVD systems.